W90P710CD Datasheet, PDF (486/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
USI Divider Register (USI_DIVIDER)
REGISTER ADDRESS R/W
DESCRIPTION
USI_Divider 0xFFF8_6204 R/W USI Clock Divider Register
31
30
29
28
27
26
Reserved
23
22
21
20
19
18
Reserved
15
14
13
12
11
10
DIVIDER[15:8]
7
6
5
4
3
2
DIVIDER[7:0]
RESET VALUE
0x0000_0000
25
24
17
16
9
8
1
0
BITS
[15:0]
DIVIDER
DESCRIPTIONS
Clock Divider Register
The value in this field is the frequency divider of the system clock pclk
to generate the serial clock on the output usi_sclk_o. The desired
frequency is obtained according to the following equation:
f _sclk
=
f _pclk
(DIVIDER +1)* 2
NOTE: Suggest DIVIDER should be at least 1.
USI Slave Select Register (USI_SSR)
REGISTER ADDRESS R/W
DESCRIPTION
USI_SSR 0xFFF8_6208 R/W USI Slave Select Register
RESET VALUE
0x0000_0000
Publication Release Date: September 19, 2006
- 487 -
Revision B2