W90P710CD Datasheet, PDF (454/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
BITS
[31:11]
[10:8]
[6:4]
[3]
[2]
[1:0]
RESERVED
PSCKFS2,
PSCKFS1,
PSCKFS0
SCKFS2,
SCKFS1,
SCKFS0
CLKSTPL
CLKSTP
RESERVED
DESCRIPTIONS
-
PSCK Frequency Selection bit 2, 1 and 0.
This selection can adjust power-on /power-offf sequence interval.
They select working clock frequency as following table. Default values
are 05h.
SCKFS0, SCKFS1,
SCKFS2
SCCLK
frequency
000
80MHz
001
40 MHz
010
20 MHz
011
10 MHz
100
5 MHz
101
2.5 MHz
110
1.25 MHz
SCCLK Frequency Selection bit 2, 1 and 0.
They select working clock frequency as following table. Default values
are 05h.
SCKFS0, SCKFS1,
SCKFS2
SCCLK
frequency
000
80MHz
001
40 MHz
010
20 MHz
011
10 MHz
100
5 MHz
101
2.5 MHz
110
1.25 MHz
Clock Stop voltage Level
0 = SCCLK stops at low if CLKSTP is also set to "0".
1 = SCCLK stops at high if CLKSTP is also set to "1".
Clock Stop control bit
Setting "1" to this bit stops SCCLK at a voltage level specified by
CLKSTPL (bit 3 of ECR).
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