W90P710CD Datasheet, PDF (20/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
5. PIN DESCRIPTION
Table 5.1 W90P710 Pins Description
PIN NAME IO TYPE
DESCRIPTION
Clock & Reset
EXTAL (15M)
I
15MHz External Clock / Crystal Input
XTAL (15M)
O 15MHz Crystal Output
EXTAL32(32.768
K)
I
32768Hz External Clock / Crystal Input(for RTC)
XTAL32(32.768K)
O 32768Hz Crystal Output(for RTC)
nRESET
IS System Reset, active-low
JTAG Interface
TCK
TMS
TDI
TDO
nTRST
IDS JTAG Test Clock, internal pull-down with 58K ohm
IUS JTAG Test Mode Select, internal pull-up with 70K ohm
IUS JTAG Test Data in, internal pull-up with 70K ohm
O JTAG Test Data out
IUS JTAG Reset, active-low, internal pull-up with 70K ohm
External Bus Interface
A [21:18]
A [17:0]
D [31:16] /
VD[23:8] /
GPIO [67:52]
D [15:0] /
nWBE [3:0] /
SDQM [3:0] /
GPIO[69:68]
nSCS [1:0]
nSRAS
nSCAS
nSWE
MCKE
MCLK
nWAIT /
GPIO[70] /
nIRQ5
nBTCS
nECS [3:0]
nOE
O Address Bus (MSB) of external memory and IO devices.
IOS Address Bus of external memory and IO devices.
Data Bus (MSB) of external memory and IO device, internal pull-up with 70K
IOU ^ohm.
General Programmable In/Out Port GPIO[67:52].
IOU Data Bus (LSB) of external memory and IO device.
Write Byte Enable for specific device (nECS [3:0]).
IOU Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low.
General Programmable In/Out Port [69:68]
O SDRAM chip select for two external banks, active-low.
O Row Address Strobe for SDRAM, active-low.
O Column Address Strobe for SDRAM, active-low.
O SDRAM Write Enable, active-low
O SDRAM Clock Enable, active-high
O System Master Clock Out, SDRAM clock, output with slew-rate control
External Wait, active-low.
This pin indicates that the external devices need more active cycle during
IOU access operation.
General Programmable In/Out Port GPIO[70]. If memory and IO devices in EBI
do not need wait request, it can be configured as GPIO[7] or nIRQ5
O ROM/Flash Chip Select, active-low.
O External I/O Chip Select, active-low.
O ROM/Flash, External Memory Output Enable, active-low.
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