W90P710CD Datasheet, PDF (235/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
SD host controller checks the associated CRC-16 bits and reports the result to SD status register.
If the data-input interrupt is enabled, an interrupt will occur when the data transfer is finished. The data
input status bit of SD status register will be set as 1 for this interrupt. Thus, the CPU can identify a
data-input interrupt by reading this bit.
When the data output enable bit of SD access control register is set, SD host controller transfers a
block of data to a specific MMC card. When the data transfer is finished, this bit is cleared to 0
automatically.
Before the data is transferred, the data to be transmitted must be stored into system memory and the
S/W must specified the starting address where the data is stored.
SD host controller will generate the associated CRC-16 bits by itself. After the data is transmitted, it
also check the CRC-status response from the SD card. The check result is stored into the SD status
register.
If the data-output interrupt is enabled, an interrupt will occur when the data transfer is finished. The
data output status bit of SD status register will be set as 1 for this interrupt. Thus, the CPU can identify
a data-output interrupt by reading this bit.
1. When the response R2 input enable bit of SD access control register is set, SD host controller
transfers a block of data to a specific SD card. When the data transfer is finished and this bit is
set, SD host controller will waits for a 136-bit R2 response from SD card. When the R2 response
is completely received, the bit is reset to 0 automatically.
y The received data of R2 response token (136-bit) is stored into the system memory, starting
from the address specified by software.
y SD host controller checks the CRC-7 and reports the result to SD status register.
2. When the 74-clock cycles output enable bit of SD access control register is set, SD host controller
generates 74 clock cycles without any CMD or DAT activity. After the 74 clock cycles have been
generated, the bit is reset to 0 automatically.
Publication Release Date: September 19, 2006
- 235 -
Revision B2