W90P710CD Datasheet, PDF (372/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
6.14 Advanced Interrupt Controller
An interrupt temporarily changes the sequence of program execution to react to a particular event
such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC
Controller, and so on. The ARM7TDMI processor provides two modes of interrupt, the Fast Interrupt
(FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception
is occurred when the nIRQ input is asserted. Similarly, the FIQ exception is occurred when the nFIQ
input is asserted. The FIQ has privilege over the IRQ and can preempt an ongoing IRQ. It is possible
to ignore the FIQ and the IRQ by setting the F and I bits in the current program status register
(CPSR).
The W90P710 incorporates the advanced interrupt controller (AIC) that is capable of dealing with
the interrupt requests from a total of 32 different sources. Currently, 31 interrupt sources are defined.
Each interrupt source is uniquely assigned to an interrupt channel. For example, the watchdog timer
interrupt is assigned to channel 1. The AIC implements a proprietary eight-level priority scheme that
differentiates the available 31 interrupt sources into eight priority levels. Interrupt sources within the
priority level 0 have the highest priority and the priority level 7 has the lowest. To work this scheme
properly, you must specify a certain priority level to each interrupt source during power-on
initialization; otherwise, the system shall behave unexpectedly. Within each priority level, interrupt
source that is positioned in a lower channel has a higher priority. Interrupt source that is active,
enabled, and positioned in the lowest channel within the priority level 0 is promoted to the FIQ.
Interrupt sources within the priority levels other than 0 can petition for the IRQ. The IRQ can be
preempted by the occurrence of the FIQ. Interrupt nesting is performed automatically by the AIC.
Though interrupt sources originated from the W90P710 itself are intrinsically high-level sensitive, the
AIC can be configured as either low-level sensitive, high-level sensitive, negative-edge triggered, or
positive-edge triggered to each interrupt source. When the W90P710 is put in the test mode, all
interrupt sources must be configured as positive-edge triggered.
The advanced interrupt controller includes the following features:
y AMBA APB bus interface
y External interrupts can be programmed as either edge-triggered or level-sensitive
y External interrupts can be programmed as either low-active or high-active
y Has flags to reflect the status of each interrupt source
y Individual mask for each interrupt source
y Proprietary 8-level interrupt scheme to ease the burden from the interrupt
y Priority methodology is adopted to allow for interrupt daisy-chaining
y Automatically masking out the lower priority interrupt during interrupt nesting
y Automatically clearing the interrupt flag when the external interrupt source is programmed to be
edge-triggered
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