W90P710CD Datasheet, PDF (459/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Continued
BITS
DESCRIPTIONS
TOC5, TOC4, TOC3 (Time Out Configuration) control 16 bit time-
out counter 1 configuration.
TOC5,
[6:4]
TOC4,
TOC3
TOC5,
TOC4,
TOC3
value
OPERATION MODE
000
16 bit counter 1 is stopped
001 Counting the value stored in register TOIR 1 is started after
001b is written in register in register TOC. An interrupt is
given if enabled, and bit TO1 is set within register SCSR
when the terminal count is reached. The counter is stopped
by writing 000b in register TOC, and should be stopped
before reloading new values in register TOC.
010 Counter 1 starts counting the content of register TOIR1 on
the first START bit (reception or transmission) detected on
the pin I/O after 010b is written in register TOC. When
counter 1 reaches its terminal count, an interrupt is given if
enable. Bit TO1 in register SCSR is set. The counter is
reloaded with TOIR1 and starts counting on each
subsequent START bit. It is possible to change the content
of TOIR1 during a count; the current count will not be
affected and the new count value will be taken into account
at the next START bit. The count is stopped by writing 000b
in register TOC,
011 Counter 1 starts counting the content of register TOIR1 on
the first START bit (reception or transmission) detected on
the pin I/O after 010b is written in register TOC. When
counter 1 reaches its terminal count, an interrupt is given if
enable. Bit TO1 in register SCSR is set. The count is
stopped by writing 000b in register TOC,
100 Same as value 000b, except that counter 1 will be stopped
at the end of the 12^th ETU following the first START bit
detected after 100b has been written in register TOC
ICE Debug mode Acknowledge enable for time-out counter 0
[3]
nDBGACK_EN0 ^{0 = When DBGACK is high, the timer clock will be held}
1 = No matter what DBGACK is high or not, the timer clock will not be
held
Publication Release Date: September 19, 2006
- 459 -
Revision B2