W90P710CD Datasheet, PDF (364/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
6.13 Timer/Watchdog Controller
6.13.1 General Timer Controller
The timer module includes two channels, TIMER0 and TIMER1, which allow you to easily implement a
counting scheme for use. The timer can perform functions like frequency measurement, event
counting, interval measurement, clock generation, delay timing, and so on. The timer possesses
features such as adjustable resolution, programmable counting period, and detailed information. The
timer can generate an interrupt signal upon timeout, or provide the current value of count during
operation.
The general TIMER Controller includes the following features
y AMBA APB interface compatible
y Two channels with a 8-bit presale counter/24-bit down counter and an interrupt request each
y Independent clock source for each channel
y Maximum uninterrupted time = (1 / 25 MHz) * (256) * (2^24), if TCLK = 25 MHz
6.13.2 Watchdog Timer
6.13.3 Timer Control Registers Map
R: read only, W: write only, R/W: both read and write
REGISTER ADDRESS R/W/C
DESCRIPTION
TCSR0 0xFFF8_1000 R/W Timer Control and Status Register 0
TCSR1 0xFFF8_1004 R/W Timer Control and Status Register 1
TICR0
0xFFF8_1008 R/W Timer Initial Control Register 0
TICR1
0xFFF8_100C R/W Timer Initial Control Register 1
TDR0
0xFFF8_1010 R Timer Data Register 0
TDR1
0xFFF8_1014 R Timer Data Register 1
TISR
0xFFF8_1018 R/W Timer Interrupt Status Register
WTCR
0xFFF8_101C R/W Watchdog Timer Control Register
RESET VALUE
0x0000_0005
0x0000_0005
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0400
Timer Control Register 0/1 (TCSR 0/1)
REGISTER ADDRESS R/W
DESCRIPTION
TCSR0 0xFFF8_1000 R/W Timer Control and Status Register 0
TCSR1 0xFFF8_1004 R/W Timer Control and Status Register 1
RESET VALUE
0x0000_0005
0x0000_0005
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