W90P710CD Datasheet, PDF (452/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Contiuned
BITS
[5]
TBRE
[4]
SBD
[3]
NSER
[2]
PBER
[1]
OER
[0]
RDR
DESCRIPTIONS
Transmitter Buffer Register Empty
In non-FIFO mode, this bit will be set to a logical 1 when a data
byte is transferred from TBR to TSR. If ETBREI of IER is a logical
1, an interrupt is generated to notify host to write the following data
bytes. In FIFO mode, this bit is set to "1" when the transmitter FIFO
is empty. It is cleared to "0" when host writes data bytes into TBR
or FIFO.
Silent Byte Detected
This bit is set to "1" to indicate that received data byte are kept in
silent state for a full byte time, including start bit, data bits, parity
bit, and stop bits. In FIFO mode, it indicates the same condition for
the data on top of FIFO. When host reads SCSR, it clears this bit
to "0".
No Stop bit Error
This bit is set to "1" to indicate that received data has no stop bit.
In FIFO mode, it indicates the same condition for the data on top of
FIFO. When host reads SCSR, it clears this bit to "0".
Parity Bit Error
This bit is set to "1" to indicate that parity bit of received data is
wrong. In FIFO mode, it indicates the same condition for the data
on top of the FIFO. When host reads SCSR, it clears this bit to "0".
Overrun Error
This bit is set to "1" to indicate previously received data is
overwritten by the next received data before it is read by host. In
FIFO mode, it indicates the same condition instead of FIFO full.
When host reads SCSR, it clears this bit to "0".
Receiver Data Ready
This bit is set to "1" to indicate received data is ready to be read by
host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is
cleared to "0".
Smart Card Host Guard Time Register (SCHI_GTR)
REGISTER
SCHI_GTR0
SCHI_GTR1
ADDRESS
0xFFF8_5018
0xFFF8_5818
R/W
R/W
R/W
DESCRIPTION
Guard time Register 0
Guard time Register 1
RESET VALUE
0x0000_0001
0x0000_0001
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