W90P710CD Datasheet, PDF (546/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
AIC Control Registers Map, continued
REGISTER ADDRESS R/W
DESCRIPTION
AIC_SCR21 0xFFF8_2054 ^R/W Source Control Register 21
AIC_SCR22 0xFFF8_2058 ^R/W Source Control Register 22
AIC_SCR23 0xFFF8_205C ^R/W Source Control Register 23
AIC_SCR24 0xFFF8_2060 ^R/W Source Control Register 24
AIC_SCR25 0xFFF8_2064 ^R/W Source Control Register 25
AIC_SCR26 0xFFF8_2068 ^R/W Source Control Register 26
AIC_SCR27 0xFFF8_206C ^R/W Source Control Register 27
AIC_SCR28 0xFFF8_2070 ^R/W Source Control Register 28
AIC_SCR29 0xFFF8_2074 ^R/W Source Control Register 29
AIC_SCR30 0xFFF8_2078 ^R/W Source Control Register 30
AIC_SCR31 0xFFF8_207C ^R/W Source Control Register 31
AIC_IRSR 0xFFF8_2100 R Interrupt Raw Status Register
AIC_IASR 0xFFF8_2104 R Interrupt Active Status Register
AIC_ISR
0xFFF8_2108 R Interrupt Status Register
AIC_IPER 0xFFF8_210C R Interrupt Priority Encoding Register
AIC_ISNR 0xFFF8_2110 R Interrupt Source Number Register
AIC_IMR 0xFFF8_2114 R Interrupt Mask Register
AIC_OISR 0xFFF8_2118 R Output Interrupt Status Register
AIC_MECR 0xFFF8_2120 W Mask Enable Command Register
AIC_MDCR 0xFFF8_2124 W Mask Disable Command Register
AIC_SSCR 0xFFF8_2128 W Source Set Command Register
AIC_SCCR 0xFFF8_212C W Source Clear Command Register
AIC_EOSCR 0xFFF8_2130 W End of Service Command Register
AIC_TEST 0xFFF8_2200 ^W
ICE/Debug mode Register
RESET VALUE
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Publication Release Date: September 19, 2006
- 547 -
Revision B2