W90P710CD Datasheet, PDF (85/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Continued.
BITS
DESCRIPTION
MCLK output delay adjustment
[3:0]
MCLK_O_D
MCLK_O_D [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Gate
Delay
P-0
P-1
P-2
P-3
P-4
P-5
P-6
P-7
MCLK_O_D [3:0]
1000
1001
1010
1011
1100
1101
1110
1111
Gate
Delay
N-0
N-1
N-2
N-3
N-4
N-5
N-6
N-7
NOTE: “P-x” means MCLKO shift “X” gates delay by refer HCLK
positive edge, “N-x” means MCLKO shift “X” gates delay by refer HCLK
negative edge. MCLK is the output pin of MCLKO, which is an internal
signal on chip.
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Publication Release Date: September 19, 2006
Revision B2