W90P710CD Datasheet, PDF (80/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Continued.
BITS
[15]
ADRS
DESCRIPTION
Address bus alignment for external I/O bank 0~3
When ADRS is set, external address (A21~A0) bus is alignment to byte
address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is
AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting.
[14:11]
tACC
Access cycles of external I/O bank 0~3
This parameter means nWE, nWBE and nOE active time clock. Detail timing
diagram please refer to Fig. 6.3.6 and 6.3.7
tACC[14:11]
0 00 0
0 00 1
0 01 0
0 01 1
0 10 0
0 10 1
0 11 0
0 11 1
MCLK
Reversed
1
2
3
4
5
6
7
tACC[14:11]
1 000
1 001
1 010
1 011
1 100
1 101
1 110
1 111
MCLK
9
11
13
15
17
19
21
23
[10:8]
Chip selection hold time of external I/O bank 0~3
This parameters control nWBE and nOE hold time. Detail timing diagram
please refer to Fig. 6.3.6 and 6.3.7
tCOH
tCOH [10:8]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MCLK
0
1
2
3
4
5
6
7
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