W90P710CD Datasheet, PDF (177/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Host Controller Interrupt Status Register
All bits are set by hardware and cleared by software.
REGISTER
ADDRESS R/W
DESCRIPTION
HcInterruptStatus 0xFFF0_500C R/W Host Controller Interrupt Status Register
RESET
VALUE
0x0000_0000
31
Reserved
23
30
OCH
22
15
14
7
6
Reserved RHSC
29
21
13
5
FNO
28
27
26
Reserved
20
19
18
Reserved
12
11
10
Reserved
4
3
2
URE
RDT
SOF
25
17
9
1
WDH
24
16
8
0
SCO
BITS
[31]
[30]
[29:7]
[6]
[5]
[4]
[3]
[2]
Reserved
OCH
RHSC
FNO
URE
RDT
SOF
DESCRIPTION
Reserved
OwnershipChange
This bit is set when the OwnershipChangeRequest bit of
HcCommandStatus is set.
Reserved
RootHubStatusChange
This bit is set when the content of HcRhStatus or the content of any
HcRhPortStatus register has changed.
FrameNumberOverflow
Set when bit 15 of FrameNumber changes value.
UnrecoverableError
This event is not implemented and is hard-coded to ‘0.’ Writes are
ignored.
ResumeDetected
Set when Host Controller detects resume signaling on a downstream
port.
StartOfFrame
Set when the Frame Management block signals a ‘Start of Frame’
event.
Publication Release Date: September 19, 2006
- 177 -
Revision B2