W90P710CD Datasheet, PDF (312/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Reserved
7
FIFO_TH
14
13
12
11
10
9
Reserved Reserved R_DMA_IRQ T_DMA_IRQ
Reserved
6
5
Reserved
4
Reserved
3
2
1
BLOCK_EN[1:0]
8
IIS_AC_PIN_
SEL
0
Reserved
BITS
[15]
[14]
[13]
[12]
[11]
[8]
[7]
[6]
Reserved
Reserved
Reserved
R_DMA_IRQ
T_DMA_IRQ
IIS_AC_PIN_SEL
FIFO_TH
Reserved
DESCRIPTIONS
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-
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When recording, when the DMA destination current address reach
the DMA destination end address or middle address, the
R_DMA_IRQ bit will be set to 1 automatically, and this bit could be
cleared to 0 by CPU. The bit is hardwired to ARM as interrupt request
signal with an inverter.
The R_DMA_IRQ bit is read/write (write 1 to clear)
Transmit DMA interrupt request bit. When DMA current address
reach the middle address (((ACTL_DESE – ACTL_DESB)-1)/2 +
ACTL_DESB) or reach the end address ACTL_DESB, the bit
T_DMA_IRQ will be set to 1, and this bit could be clear to 0 by write
“1” by CPU. And the bit is hardwired to ARM as interrupt request
signal with an inverter.
The T_DMA_IRQ bit is read/write (write 1 to clear).
IIS or AC-link pin selection
• If IIS_AC_PIN_SEL = 0, the pins select IIS
• If IIS_AC_PIN_SEL = 1, the pins select AC-link
The IIS_AC_PIN_SEL bis is read/write
FIFO threshold control bit
• If FIFO_TH=0, the FIFO threshold is 8 level
• If FIFO_TH=1, the FIFO threshold is 4 level
The FIFO_TH bit is read/write
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