W90P710CD Datasheet, PDF (488/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3)
REGISTER
USI_RX0
USI_RX1
USI_RX2
USI_RX3
ADDRESS R/W
DESCRIPTION
0xFFF8_6210 R USI Data Receive Register 0
0xFFF8_6214 R USI Data Receive Register 1
0xFFF8_6218 R USI Data Receive Register 2
0xFFF8_621C R USI Data Receive Register 3
31
30
29
28
27
26
Rx [31:24]
23
22
21
20
19
18
Rx [23:16]
15
14
13
12
11
10
Rx [15:8]
7
6
5
4
3
2
Rx [7:0]
RESET VALUE
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
25
24
17
16
9
8
1
0
BITS
[31:0]
DESCRIPTIONS
Data Receive Register
The Data Receive Registers hold the value of received data of the last
executed transfer. Valid bits depend on the transmit bit length field in the
CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and
Rx
CNTRL[Tx_NUM] is set to 0x0, bit Rx0[7:0] holds the received data.
NOTE: The Data Receive Registers are read only registers. A Write to
these registers will actually modify the Data Transmit Registers because
those registers share the same FFs.
Data Transmit Register 0/1/2/3 (Tx0/1/2/3)
REGISTER
USI_TX0
USI_TX1
USI_TX2
USI_TX3
ADDRESS R/W
DESCRIPTION
0xFFF8_6210 W USI Data Transmit Register 0
0xFFF8_6214 W USI Data Transmit Register 1
0xFFF8_6218 W USI Data Transmit Register 2
0xFFF8_621C W USI Data Transmit Register 3
RESET VALUE
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Publication Release Date: September 19, 2006
- 489 -
Revision B2