W90P710CD Datasheet, PDF (242/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
SD global Interrupt Status Register (SDGISR)
REGISTER ADDRESS
SDGISR 0xFFF0_7010
R/W
R/W
DESCRIPTION
SD Global Interrupt Status Register
RESET VALUE
0x0000_0000
31
23
15
7
Reserved
30
22
14
6
ERRINT
29
21
13
5
DRdINT
28
27
Reserved
20
19
Reserved
12
11
Reserved
4
3
DWrINT SDHIINT
26
18
10
2
Reserved
25
17
9
1
Reserved
24
16
8
0
SDGINT
BITS
[31:7]
[6]
Reserved
ERRINT
[5]
DRdINT
[4]
DWrINT
[3]
SDHIINT
[0]
SDGINT
DESCRIPTIONS
-
Bus Error Interrupt Status
DMA Read Interrupt Status
This bit indicates the DMA read transfer (from external SDRAM to
internal buffer) has finished.
1’b0: No DMA read transfer completion
1’b1: DMA read transfer completed
DMA Write Interrupt Status
This bit indicates the DMA write transfer (from internal buffer to external
SDRAM) has finished.
1’b0: No DMA write transfer completion
1’b1: DMA write transfer completed
Secure Digital Host Controller Interface Interrupt Status
This bit indicates there is an interrupt status from Secure Digital host
controller.
1’b0: No interrupt status from Secure Digital host controller interface.
1’b1: There is an interrupt status from Secure Digital host controller
Interface
SD Host Global Interrupt Status
This bit is the wired-OR of SDHINT, DWrINT and DRdINT.
1’b0: No SD host controller interrupt notification
1’b1: There is an SD host controller interrupt status
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