W90P710CD Datasheet, PDF (241/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
BITS
[31:7]
Reserved
[6]
ERRIEN
[5]
DRdIEN
[4]
DWrIEN
[3]
SDHIIEN
[0]
SDGIEN
DESCRIPTIONS
-
Bus Error Interrupt Enable
DMA Read Interrupt Enable
This bit controls the SD host controller interrupt generation from the
interrupt of the DMA read operation.
1’b0: DMA read interrupt is masked from SD host controller interrupt
generation
1’b1: DMA read interrupt can participate in SD host controller interrupt
generation
DMA Write Interrupt Enable
This bit controls the SD host controller interrupt generation from the
interrupt of the DMA write operation.
1’b0: DMA write interrupt is masked from SD host controller interrupt
generation
1’b1: DMA write interrupt can participate in SD host controller interrupt
generation
Secure Digital Host Controller Interface Interrupt Enable
This bit controls the SD host controller interrupt generation from the
interrupt of Secure Digital host controller.
1’b0: Secure Digital host controller’s interrupt is masked from SD host
controller interrupt generation
1’b1: Secure Digital host controller’s interrupt can participate in SD host
controller interrupt generation
SD Host Global Interrupt Enable
This bit controls the interrupt generation of SD host controller Globally.
1’b0: Disable SDI host controller interrupt generation globally
1’b1: Enable SD host controller interrupt generation globally
Publication Release Date: September 19, 2006
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Revision B2