W90P710CD Datasheet, PDF (58/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
EXTAL
FIN
Input Divider
INDV1[4:0]
(NR)
PLL1
PFD
Charge
Pump
VCO
Output _480MHz
Divider
(NO) ^FOUT
FBDV1[8:0]
Feedback
Divider
(NF)
to LCD controller
to Audio Controller
OTDV1[1:0]
Fig 6.2.8.2 LCD PLL block diagram
The formula of output clock of PLL is:
FOUT
=
FIN
∗
NF
NR
∗
1
NO
FOUT：Output clock of Output Divider
FIN：External clock into the Input Divider
NR：Input divider value (NR = INDV1 + 2)
NF：Feedback divider value (NF = FBDV1 + 2)
NO：Output divider value (NO = OTDV1)
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