W90P710CD Datasheet, PDF (306/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
6.10.3.8 Palette SRAM Build In Self-Test
Lookup Table SRAM Build In Self Test Register (BIST)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
BIST
0xFFF0_80D0 R/W Lookup Table SRAM Build In Self Test 0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
FAIL
FINISH
BISTEN
BITS
[31:3]
Reserved
[2]
FAIL
[1]
FINISH
[0]
BISTEN
DESCRIPTIONS
Reserved
BIST Fail indicator
0 = SRAM BIST not fail
1 = SRAM BIST fail
BIST Finish Status (Read Only)
0 = When BIST enabled, this value means BIST not finished
1 = When BIST enabled, this value means BIST finished, and FAIL
can be referenced
BIST Mode Enable
0 = SRAM is in normal operation.
1 = BIST enabled, SRAM is under BIST test
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