W90P710CD Datasheet, PDF (234/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
6.9 SD Host Controller
The SD host controller of W90P710 supports Secure Digital card devices (SD, MMC). The SD host-
controller also supports DMA function to reduce the intervention of CPU for data transfer between
flash memory card and system memory.
There are two 512B internal buffers embedded in the SD host controller to buffer the data temporally
for DMA transfer between flash memory card and system memory.
The SD host controller features are shown as below:
y Directly connect to Secure Digital (SD, MMC) flash memory card.
y Supports DMA function to accelerate the data transfer between the internal buffer, external
SDRAM, and flash memory card.
y Two 512 bytes internal buffers are embedded inside of the SD host controller.
y No SPI mode.
6.9.1 Functional Description
SD host controller provides three signals, CLK, CMD and DAT[3:0], to all SD cards. CLK is a clock
output signal. CMD and DAT[3:0] are bi-direction command and data signals, respectively.
The frequency of CLK is equal to (engine clock frequency)/(SD_CLK+1), where SD_CLK is the value
of the SD clock control register. To save power, CLK is active only when there are activities between
SD host controller and SD cards. Otherwise, CLK keeps inactive state (LOW).
According to the SD specification, SD host controller provides several operations to communicate with
SD Cards efficiently. The CPU writes to the SD access control register to setup the operations.
When the command output enable bit of SD access control register is set, SD host controller transfers
a 48-bit command to one or more SD cards. When the transfer is done, this bit is reset to 0
automatically.
For a 48-bits command, the 6-bits command number is coming from SD CMD code register and the
32-bits command argument is coming from SD command argument 1-4 registers. All other bits
(including start bit, end bit and the CRC-7bits) are generated by SD host controller H/W circuit.
When the response input enable bit of SD access control register is set, SD host controller waits for a
48-bit response form one or more SD card. When a 48-bit response is received, this bit is reset to 0
automatically.
The first 40 bits of the received response are stored into SD received response token1 – 5 registers.
The last 8 bits are CRC-7 bits and end bit. SD host controller H/W circuit checks CRC-7 and reports
the result to SD status register.
When the data input enable bit of SD access control register is set, SD host controller waits for a block
of data from a specific SD card. When a block of data is received, this bit is cleared to 0 automatically.
The received block of data is stored into the system memory and the address is starting from the
address specified by S/W.
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