W90P710CD Datasheet, PDF (43/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Table 6.2.9 and Table 6.2.10
Using little-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0,4,8,C X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table6.2.9 Word access write operation with little Endian
Access Operation
Write Operation (CPU Register Î External Memory)
XD Width
Word
Half Word
Byte
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
31 0
ABCD
SA
WA
WA
WA
Bit Number
SD
31 0
ABCD
31 0
AB CD
31 0
ABCD
Bit Number
31 0
15 0
15 0
70
70
70
70
ED
ABCD
CD
AB
D
C
B
A
XA
WA
WA
WA+2
WA
WA+1
WA+2
WA+3
nWBE [3-0] /
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
AAAA
31 0
ABCD
31 0
ABCD
XXAA
15 0
CD
15 0
CD
1st write
XXAA
15 0
AB
15 0
AB
2nd write
XXXA
70
D
70
D
1st write
XXXA
70
C
70
C
2nd write
XXXA
70
B
70
B
3rd write
XXXA
70
A
70
A
4th write
Table6.2.10 Word access read operation with Little Endian
Access Operation
Read Operation (CPU Register Í External Memory)
XD Width
Word
Half Word
Byte
Bit Number
CPU Reg Data
31 0
ABCD
31 0
ABCD
31 0
ABCD
SA
WA
WA
WA
Bit Number
SD
Bit Number
ED
31 0
ABCD
31 0
ABCD
31 0
AB CD
31 0
XX CD
31 0
AB CD
31 0
XXXD
31 0
ABCD
31 0 31 0
XXCD XBCD
XA
WA
WA
WA+2
WA
WA+1
WA+2
31 0
ABCD
WA+3
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
AAAA
31 0
ABCD
31 0
ABCD
XXAA
15 0
CD
15 0
CD
1st read
XXAA
15 0
AB
15 0
AB
2nd read
XXXA
70
D
70
D
1st read
XXXA
70
C
70
C
2nd read
XXXA
70
B
70
B
3rd read
XXXA
70
A
70
A
4th read
- 43 -
Publication Release Date: September 19, 2006
Revision B2