W90P710CD Datasheet, PDF (245/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Continued.
BITS
[5]
74CLK_OE
[4]
R2_EN
[3]
DO_EN
[2]
DI_EN
[1]
RI_EN
[0]
CO_EN
DESCRIPTIONS
74 Clock Cycle Output Enable
0=Disable
1=Enable, SD host controller outputs 74 clock cycles
When the operation is finished, this bit is automatically cleared to “0”
by H/W circuit.
Response R2 Input Enable
0=Disable
1=Enable, SD host controller will wait to receive a response R2 from
DS card and store the response data into flash buffer.
When the R2 response operation is finished, this bit is automatically
cleared to “0” by H/W circuit.
Data Output Enable
0=Disable
1=Enable, SD host controller will transfer a single block data and the
CRC-16 code to SD card.
When the data output operation is finished, this bit is automatically
cleared to “0” by H/W circuit.
Data Input Enable
0=Disable
1=Enable, SD host controller will wait to receive a single block data
and the CRC-16 code from SD card.
When the data input operation is finished, this bit is automatically
cleared to “0” by H/W circuit.
Response Input Enable
0=Disable
1=Enable, SD host controller will wait to receive a response from SD
card.
When the response operation is finished, this bit is automatically
cleared to “0” by H/W circuit.
Command Output Enable
0=Disable
1=Enable, SD host controller will transfer a command to SD card.
When the command operation is finished, this bit is automatically
cleared to “0” by H/W circuit.
Publication Release Date: September 19, 2006
- 245 -
Revision B2