W90P710CD Datasheet, PDF (132/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
RXMS
7
6
5
4
3
2
1
0
RXMS
BITS
[31:16]
Reserved
[15:0]
RXMS
DESCRIPTIONS
-
The Maximum Receive Frame Length defines the
maximum frame length for received frame. If the frame
length of received frame is greater than RXMS, and bit
EnDFO of MIEN register is also enabled, the bit DFOI of
MISTA register is set and the Rx interrupt is triggered.
It is recommended that only use RXMS to qualify the length
of received frame while S/W wants to receive a frame which
length is greater than 1518 bytes.
MAC Interrupt Enable Register (MIEN)
The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR
for frame reception and TXINTR for frame transmission, are generated from EMC to CPU.
REGISTER
MIEN
ADDRESS R/W
DESCRIPTION
0xFFF0_30AC R/W MAC Interrupt Enable Register
RESET VALUE
0x0000_0000
31
23
EnTDU
15
Reserved
7
EnMMP
30
22
EnLC
14
EnCFR
6
EnRP
29
28
27
Reserved
21
20
19
EnTXABT EnNCS EnEXDEF
13
12
11
Reserved
EnRxBErr
5
4
3
EnALIE EnRXGD EnPTLE
26
18
EnTXCP
10
EnRDU
2
EnRXOV
25
17
EnTXEMP
9
EnDEN
1
EnCRCE
24
EnTxBErr
16
EnTXINTR
8
EnDFO
0
EnRXINTR
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