W90P710CD Datasheet, PDF (522/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
7.3.5 LCD Interface AC Characteristics
VCLK
VSYNC
HSYNC
VDEN
VD[23:0]
T_PIXCLK
T_DELAY
valid data
T_HOLD
SYMBOLS
DESCRIPTION
MIN
T_PIXCLK
T_DELAY
Pixel clock frequency
-
VSYNC, HSYNC, VDEN and VD[23:0] output delay from
VCLK rising edge
5
T_HOLD
VSYNC, HSYNC, VDEN and VD[23:0] output data hold
time from VCLK rising edge
0
MAX
40
15
5
UNIT
MHz
ns
ns
Publication Release Date: September 19, 2006
- 523 -
Revision B2