W90P710CD Datasheet, PDF (263/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
BITS
[31:20]
[18]
[17]
[16]
[15:6]
[5]
[4]
[3]
[2]
[1]
[0]
Reserved
UNDRIS2
UNDRIS1
AHBERIS
Reserved
HSIS
VSIS
VLFINIS2
VFFINIS2
VLFINIS1
VFFINIS1
DESCRIPTIONS
Reserved
FIFO2 have no data for output to Panel
FIFO1 have no data for output to Panel
AHB master bus error status
Reserved
Timing Generator output a HSYNC pulse
Timing Generator output a VSYNC pulse
FIFO2 transfer one line stream complete
FIFO2 transfer one frame stream complete
FIFO1 transfer one line stream complete
FIFO1 transfer one frame stream complete
LCD Controller is an AHB Master at AMBA and fetching video data from an AHB Slave such as SDRAM
or FLASH memory. If AHB Slave response ERROR for LCD Controller’s data request, AHBERIS will be
set.
If the data rate of output to LCD Panel is too fast and the data rate of fetch data from AMBA is too slow;
there are no data in FIFO for LCD Panel’s request, UNDRISx will be set. LCD Timing Generation register
need to be re-configured.
HSIS and VSIS provide information for firmware to know the status of LCD Panel.
VLFINISx and VFFINISx provide information for firmware to know how much data FIFO have fetched.
LCD Interrupt Clear Register (LCDINTC)
REGISTER
ADDRESS
R/W
DESCRIPTION
LCDINTC 0xFFF0_800C W LCD interrupt clear
RESET VALUE
0x0000_0000
Publication Release Date: September 19, 2006
- 263 -
Revision B2