W90P710CD Datasheet, PDF (376/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
ACTION
NORMAL MODE
ICE/DEBUG MODE
Calculate active interrupt
Read AIC_IPER
Read AIC_IPER
Determine and return the vector of the active interrupt Read AIC_IPER
Read AIC_IPER
Push on internal stack the current priority level
Read AIC_IPER
Write AIC_IPER
Acknowledge the interrupt (Note 1)
Read AIC_IPER
Write AIC_IPER
No effect (Note 2)
Read AIC_IPER
Notes:
y NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level
sensitive.
y Note that software which has been written and debugged using this mode will run correctly in
normal mode without modification. However, in normal mode writing to AIC_IPER has no effect
and can be removed to optimize the code
6.14.2 AIC Registers Map
REGISTER ADDRESS R/W
DESCRIPTION
AIC_SCR1 0xFFF8_2004 ^R/W Source Control Register 1
AIC_SCR2 0xFFF8_2008 ^R/W Source Control Register 2
AIC_SCR3 0xFFF8_200C ^R/W Source Control Register 3
AIC_SCR4 0xFFF8_2010 ^R/W Source Control Register 4
AIC_SCR5 0xFFF8_2014 ^R/W Source Control Register 5
AIC_SCR6 0xFFF8_2018 ^R/W Source Control Register 6
AIC_SCR7 0xFFF8_201C ^R/W Source Control Register 7
AIC_SCR8 0xFFF8_2020 ^R/W Source Control Register 8
AIC_SCR9 0xFFF8_2024 ^R/W Source Control Register 9
AIC_SCR10 0xFFF8_2028 ^R/W Source Control Register 10
AIC_SCR11 0xFFF8_202C ^R/W Source Control Register 11
AIC_SCR12 0xFFF8_2030 ^R/W Source Control Register 12
AIC_SCR13 0xFFF8_2034 ^R/W Source Control Register 13
AIC_SCR14 0xFFF8_2038 ^R/W Source Control Register 14
AIC_SCR15 0xFFF8_203C ^R/W Source Control Register 15
RESET VALUE
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
0x0000_0047
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