W90P710CD Datasheet, PDF (176/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Host Controller Command Status Register
REGISTER
ADDRESS
HcCommandStatus 0xFFF0_5008
R/W
DESCRIPTION
R/W Host Controller Command Status Register
RESET
VALUE
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
OCR
BLF
CLF
HCR
BITS
[31:18]
[17:16]
[15:4]
[3]
[2]
[1]
[0]
Reserved
SOC
Reserved
OCR
BLF
CLF
HCR
DESCRIPTION
Reserved
ScheduleOverrunCount
This field is increment every time the SchedulingOverrun bit in
HcInterruptStatus is set. The count wraps from ‘11’ to ‘00.’
Reserved. Read/Write 0's
OwnershipChangeRequest
When set by software, this bit sets the OwnershipChange field in
HcInterruptStatus. The bit is cleared by software.
BulkListFilled
Set to indicate there is an active ED on the Bulk List. The bit may be
set by either software or the Host Controller and cleared by the Host
Controller each time it begins processing the head of the Bulk List.
ControlListFilled
Set to indicate there is an active ED on the Control List. It may be set
by either software or the Host Controller and cleared by the Host
Controller each time it begins processing the head of the Control List.
HostControllerReset
This bit is set to initiate the software reset. This bit is cleared by the
Host Controller, upon completed of the reset operation.
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