W90P710CD Datasheet, PDF (179/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Continued.
BITS
[5]
FNOE
[4]
UREE
[3]
RDTE
[2]
SOFE
[1]
WDHE
[0]
SCHOE
DESCRIPTION
FrameNumberOverflowEnable
0: Ignore
1: Enable interrupt generation due to Frame Number Overflow.
UnrecoverableErrorEnable
This event is not implemented. All writes to this bit are ignored.
ResumeDetectedEnable
0: Ignore
1: Enable interrupt generation due to Resume Detected.
StartOfFrameEnable
0: Ignore
1: Enable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable
0: Ignore
1: Enable interrupt generation due to Write-back Done Head.
SchedulingOverrunEnable
0: Ignore
1: Enable interrupt generation due to Scheduling Overrun.
Host Controller Interrupt Disable Register
Writing a ‘1’ to a bit in this register clears the corresponding bit, while writing a ‘0’ to a bit leaves the bit
unchanged.
REGISTER
ADDRESS R/W
DESCRIPTION
RESET
VALUE
HcInterruptEnable 0xFFF0_5014 R/W Host Controller Interrupt Disable Register 0x0000_0000
31
30
MIE
OCE
23
22
15
14
7
Reserved
6
RHSCE
29
21
13
5
FNOE
28
27
26
Reserved
20
19
18
Reserved
12
11
10
Reserved
4
UREE
3
RDTE
2
SOFE
25
17
9
1
WDHE
24
16
8
0
SCHOE
Publication Release Date: September 19, 2006
- 179 -
Revision B2