W90P710CD Datasheet, PDF (535/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
EMC Registers Map, continued
REGISTER ADDRESS
CAM12M 0xFFF0_3068
CAM12L 0xFFF0_306C
CAM13M 0xFFF0_3070
CAM13L
0xFFF0_3074
CAM14M 0xFFF0_3078
CAM14L 0xFFF0_307C
CAM15M 0xFFF0_3080
CAM15L
0xFFF0_3084
TXDLSA
0xFFF0_3088
RXDLSA 0xFFF0_308C
MCMDR
MIID
MIIDA
FFTCR
TSDR
RSDR
DMARFC
MIEN
MISTA
MGSTA
MPCNT
MRPC
MRPCC
MREPC
DMARFS
0xFFF0_3090
0xFFF0_3094
0xFFF0_3098
0xFFF0_309C
0xFFF0_30A0
0xFFF0_30A4
0xFFF0_30A8
0xFFF0_30AC
0xFFF0_30B0
0xFFF0_30B4
0xFFF0_30B8
0xFFF0_30BC
0xFFF0_30C0
0xFFF0_30C4
0xFFF0_30C8
CTXDSA 0xFFF0_30CC
CTXBSA 0xFFF0_30D0
CRXDSA 0xFFF0_30D4
CRXBSA 0xFFF0_30D8
R/W
DESCRIPTION
RESET VALUE
R/W CAM12 Most Significant Word Register
0x0000_0000
R/W CAM12 Least Significant Word Register
0x0000_0000
R/W CAM13 Most Significant Word Register
0x0000_0000
R/W CAM13 Least Significant Word Register
0x0000_0000
R/W CAM14 Most Significant Word Register
0x0000_0000
R/W CAM14 Least Significant Word Register
0x0000_0000
R/W CAM15 Most Significant Word Register
0x0000_0000
R/W CAM15 Least Significant Word Register
0x0000_0000
R/W Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC
R/W
Receive Descriptor
Register
Link
List
Start
Address _{0xFFFF_FFFC}
R/W MAC Command Register
0x0000_0000
R/W MII Management Data Register
0x0000_0000
R/W MII Management Control and Address Register 0x0090_0000
R/W FIFO Threshold Control Register
0x0000_0101
W Transmit Start Demand Register
Undefined
W Receive Start Demand Register
Undefined
R/W Maximum Receive Frame Control Register
0x0000_0800
R/W MAC Interrupt Enable Register
0x0000_0000
R/W MAC Interrupt Status Register
0x0000_0000
R/W MAC General Status Register
0x0000_0000
R/W Missed Packet Count Register
0x0000_7FFF
R MAC Receive Pause Count Register
0x0000_0000
R MAC Receive Pause Current Count Register 0x0000_0000
R MAC Remote Pause Count Register
0x0000_0000
R/W DMA Receive Frame Status Register
0x0000_0000
R
Current Transmit
Register
Descriptor
Start
Address _{0x0000_0000}
R Current Transmit Buffer Start Address Register 0x0000_0000
R
Current Receive
Register
Descriptor
Start
Address _{0x0000_0000}
R Current Receive Buffer Start Address Register 0x0000_0000
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