MC68HC912DG128 Datasheet, PDF (83/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Operating Modes
Internal Resource Mapping
INITRG — Initialization of Internal Register Position Register
Bit 7
6
5
4
3
2
REG15 REG14 REG13 REG12 REG11
0
RESET:
0
0
0
0
0
0
$0011
1
Bit 0
0
MMSWAI
0
0
REG[15:11] — Internal register map position
These bits specify the upper five bits of the 16-bit registers address.
Normal modes: write once; special modes: write anytime. Read
anytime.
MMSWAI — Memory Mapping Interface Stop in Wait Control
This bit controls access to the memory mapping interface when in
Wait mode.
Normal modes: write anytime; special modes: write never. Read
anytime.
0 = Memory mapping interface continues to function during Wait
mode.
1 = Memory mapping interface access is shut down during Wait
mode.
5.5.2 RAM Mapping
The MC68HC912DG128 has 8K bytes of fully static RAM that is used for
storing instructions, variables, and temporary data during program
execution. Since the RAM is actually implemented with two 4K RAM
arrays, any misaligned word access between last address of first 4K
RAM and first address of second 4K RAM will take two cycles instead of
one. After reset, RAM addressing begins at location $2000 but can be
assigned to any 8K byte boundary within the standard 64K byte address
space. Mapping of internal RAM is controlled by three bits in the INITRM
register.
MC68HC912DG128 — Rev 3.0
MOTOROLA
Operating Modes
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Technical Data
83