MC68HC912DG128 Datasheet, PDF (330/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
MSCAN Controller
The clock source bit (CLKSRC) in the msCAN12 module control register
(CMCR1) (see msCAN12 Bus Timing Register 0 (CBTR0)) defines
whether the msCAN12 is connected to the output of the crystal oscillator
(EXTALi) or to a clock twice as fast as the system clock (ECLK).
The clock source has to be chosen such that the tight oscillator tolerance
requirements (up to 0.4%) of the CAN protocol are met. Additionally, for
high CAN bus rates (1 Mbps), a 50% duty cycle of the clock is required.
NOTE:
If the system clock is generated from a PLL, it is recommended to select
the crystal clock source rather than the system clock source due to jitter
considerations, especially at faster CAN bus rates.
For microcontrollers without the CGM module, CGMCANCLK is driven
from the crystal oscillator (EXTALi).
A programmable prescaler is used to generate out of msCANCLK the
time quanta (Tq) clock. A time quantum is the atomic unit of time handled
by the msCAN12.
fT_q = ^{f--C-P----G-r--e--M--s---cC-----}_â‹^{A---v-N--a---C-l--u--L-e---K--}
A bit time is subdivided into three segments⁽¹⁾:
• SYNC_SEG: This segment has a fixed length of one time
quantum. Signal edges are expected to happen within this section.
• Time segment 1: This segment includes the PROP_SEG and the
PHASE_SEG1 of the CAN standard. It can be programmed by
setting the parameter TSEG1 to consist of 4 to 16 time quanta.
• Time segment 2: This segment represents the PHASE_SEG2 of
the CAN standard. It can be programmed by setting the TSEG2
parameter to be 2 to 8 time quanta long.
The synchronization jump width can be programmed in a range of 1 to 4
time quanta by setting the SJW parameter.
Technical Data
330
1. For further explanation of the under-lying concepts please refer to ISO/DIS 11519-1, Section
10.3.
MC68HC912DG128 — Rev 3.0
MSCAN Controller
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