MC68HC912DG128 Datasheet, PDF (110/452 Pages) Motorola, Inc – Microcontrollers

Flash Memory
Freescale Semiconductor, Inc.
7.7 Flash EEPROM Registers
Each 32K byte Flash EEPROM module has a set of registers. The
register space $00F4-$00F7 is in a register space window of four pages.
Each register page of four bytes maps the register space for each Flash
module and each page is selected by the PPAGE register. See
Operating Modes.
FEELCK — Flash EEPROM Lock Control Register
$00F4
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
LOCK
RESET:
0
0
0
0
0
0
0
0
In normal modes the LOCK bit can only be written once after reset.
LOCK — Lock Register Bit
0 = Enable write to FEEMCR register
1 = Disable write to FEEMCR register
FEEMCR — Flash EEPROM Module Configuration Register
$00F5
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
BOOTP
RESET:
0
0
0
0
0
0
0
1
This register controls the operation of the Flash EEPROM array.
BOOTP cannot be changed when the LOCK control bit in the
FEELCK register is set or if ENPE in the FEECTL register is set.
BOOTP — Boot Protect
The boot blocks are located at $E000–$FFFF and $A000–$BFFF for
odd program pages for each Flash EEPROM module. Since boot
programs must be available at all times, the only useful boot block is
at $E000–$FFFF location. All paged boot blocks can be used as
protected program space if desired.
0 = Enable erase and program of 8K byte boot block
1 = Disable erase and program of 8K byte boot block
Technical Data
110
MC68HC912DG128 — Rev 3.0
Flash Memory
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