MC68HC912DG128 Datasheet, PDF (348/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
MSCAN Controller
NOTE: The CTFLG register is held in the reset state if the SFTRES bit in
CMCR0 is set.
17.13.9 msCAN12 Transmitter Control Register (CTCR)
Bit 7
6
5
4
3
CTCR R
0
0
ABTRQ2 ABTRQ1 ABTRQ0
$0107 W
RESET
0
0
0
0
0
2
TXEIE2
0
1
TXEIE1
0
Bit 0
TXEIE0
0
ABTRQ2 – ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that a scheduled message
buffer (TXEx = 0) shall be aborted. The msCAN12 grants the request
if the message has not already started transmission or if the
transmission is not successful (lost arbitration or error). When a
message is aborted, the associated TXE and the Abort Acknowledge
flag (ABTAK, see msCAN12 Transmitter Flag Register (CTFLG)) are
set and an TXE interrupt is generated if enabled. The CPU cannot
reset ABTRQx. ABTRQx is cleared implicitly whenever the
associated TXE flag is set.
0 = No abort request.
1 = Abort request pending.
NOTE: The software must not clear one or more of the TXE flags in CTFGL and
simultaneously set the respective ABTRQ bit(s).
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
0 = No interruptis generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
event results in a transmitter empty interrupt.
NOTE: The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Technical Data
348
MC68HC912DG128 — Rev 3.0
MSCAN Controller
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