MC68HC912DG128 Datasheet, PDF (281/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Inter-IC Bus
IIC Register Descriptions
15.6 IIC Register Descriptions
.
IBAD — IIC Bus Address Register
RESET:
Bit 7
ADR7
0
6
ADR6
0
5
ADR5
0
4
ADR4
0
3
ADR3
0
2
ADR2
0
1
ADR1
0
Bit 0
0
0
$00E0
Read and write anytime
This register contains the address the IIC will respond to when
addressed as a slave; note that it is not the address sent on the bus
during the address transfer
ADR7–ADR1 — Slave Address
Bit 1 to bit 7 contain the specific slave address to be used by the IIC
module.
The default mode of IIC is slave mode for an address match on the
bus.
IBFD — IIC Bus Frequency Divider Register
$00E1
Bit 7
6
5
4
3
2
1
Bit 0
0
0
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
RESET:
0
0
0
0
0
0
0
0
Read and write anytime
IBC5–IBC0 — IIC Bus Clock Rate 5–0
This field is used to prescale the clock for bit rate selection. The bit
clock generator is implemented as a prescaled shift register - IBC5-3
select the prescaler divider and IBC2-0 select the shift register tap
point. The IBC bits are decoded to give the Tap and Prescale values
as shown in Table 15-1.
MC68HC912DG128 — Rev 3.0
MOTOROLA
Inter-IC Bus
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Technical Data
281