MC68HC912DG128 Datasheet, PDF (352/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
MSCAN Controller
CIDMR5 to ‘don’t care. To receive standard identifiers in 16 bit filter
mode it is required to program the last three bits (AM2–AM0) in the mask
registers CIDMR1, CIDMR3, CIDMR5 and CIDMR7 to ‘don’t care
CIDMR0 R
$0114 W
CIDMR1 R
$0115 W
CIDMR2 R
$0116 W
CIDMR3 R
$0117 W
RESET
CIDMR4 R
$011C W
CIDMR5 R
$011D W
CIDMR6 R
$011E W
CIDMR7 R
$011F W
RESET
Figure 17-16. Identifier Mask Registers (1st bank)
Bit 7
6
5
4
3
2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
-
-
-
-
-
-
Figure 17-17. Identifier Mask Registers (2nd bank)
Bit 7
6
5
4
3
2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
-
AM6
-
AM5
-
AM4
-
AM3
-
AM2
-
1
AM1
AM1
AM1
AM1
-
1
AM1
AM1
AM1
AM1
-
Bit 0
AM0
AM0
AM0
AM0
-
Bit 0
AM0
AM0
AM0
AM0
-
AM7 – AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared this indicates that the
corresponding bit in the identifier acceptance register must be the
same as its identifier bit, before a match is detected. The message is
accepted if all such bits match. If a bit is set, it indicates that the state
of the corresponding bit in the identifier acceptance register does not
affect whether or not the message is accepted.
0 = Match corresponding acceptance code register and identifier bits.
1 = Ignore corresponding acceptance code register bit.
NOTE: The CIDMR0–7 registers can only be written if the SFTRES bit in
CMCR0 is set.
Technical Data
352
MC68HC912DG128 — Rev 3.0
MSCAN Controller
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