MC68HC912DG128 Datasheet, PDF (180/452 Pages) Motorola, Inc – Microcontrollers

Clock Functions
Freescale Semiconductor, Inc.
11.8 Clock Divider Chains
Figure 11-6, Figure 11-7, Figure 11-8, and Figure 11-9 summarize the
clock divider chains for the various peripherals on the
68HC(9)12DG128.
BCSP BCSS
1:x
PHASE
LOCK
LOOP
PLLCLK
SYSCLK
T CLOCK
÷2
GENERATOR
TCLKs
TO CPU
EXTAL
EXTALi
XTAL
REDUCED
CONSUMPTION
OSCILLATOR
EXTALi
EXTALi
BCSP BCSS
0:0
BCSP BCSS
0:1
CLKSRC = 1
CLKSRC = 0
SLOW MODE
CLOCK
DIVIDER
SLWCLK
÷2
÷2
E AND P
CLOCK
GENERATOR
ECLK
PCLK
TO
BUSES,
SPI,
PWM,
ATD0, ATD1
SYNC
SYNC
MCS = 0
MCS = 1
CLKSW = 0
TO
MSCAN
TO
MCLK _{SCI0, SCI1,}
ECT
XCLK
TO
RTI, COP
TO CAL
CLKSW = 1
BDMCLK
TO BDM
TO CLOCK
MONITOR
Technical Data
180
Figure 11-6. Clock Generation Chain
MC68HC912DG128 — Rev 3.0
Clock Functions
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA