MC68HC912DG128 Datasheet, PDF (376/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
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18.5.1.1 SWI Dual Address Mode
In this mode, dual address-only breakpoints can be set, each of which
cause a software interrupt. This is the only breakpoint mode which can
force the CPU to execute a SWI. Program fetch tagging is the default in
this mode; data breakpoints are not possible. In the dual mode each
address breakpoint is affected by the BKPM bit and the BKALE bit. The
BKxRW and BKxRWE bits are ignored. In dual address mode the
BKDBE becomes an enable for the second address breakpoint. The
BKSZ8 bit will have no effect when in a dual address mode.
18.5.1.2 BDM Full Breakpoint Mode
A single full feature breakpoint which causes the part to enter
background debug mode. BDM mode may be entered by a breakpoint
only if an internal signal from the BDM indicates background debug
mode is enabled.
• Breakpoints are not allowed if the BDM mode is already active.
Active mode means the CPU is executing out of the BDM ROM.
• BDM should not be entered from a breakpoint unless the ENABLE
bit is set in the BDM. This is important because even if the
ENABLE bit in the BDM is negated the CPU actually does execute
the BDM ROM code. It checks the ENABLE and returns if not set.
If the BDM is not serviced by the monitor then the breakpoint
would be re-asserted when the BDM returns to normal CPU flow.
• There is no hardware to enforce restriction of breakpoint operation
if the BDM is not enabled.
18.5.1.3 BDM Dual Address Mode
Dual address-only breakpoints, each of which cause the part to enter
background debug mode. In the dual mode each address breakpoint is
affected, consistent across modes, by the BKPM bit, the BKALE bit, and
the BKxRW and BKxRWE bits. In dual address mode the BKDBE
becomes an enable for the second address breakpoint. The BKSZ8 bit
will have no effect when in a dual address mode. BDM mode may be
Technical Data
376
MC68HC912DG128 — Rev 3.0
Development Support
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