MC68HC912DG128 Datasheet, PDF (291/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Inter-IC Bus
IIC Programming Examples
An example of a program which generates the START signal and
transmits the first byte of data (slave address) is shown below:
CHFLAG
TXSTART
IBFREE
BRSET
BSET
MOVB
BRCLR
IBSR,#$20,*
IBCR,#$30
CALLING,IBDR
IBSR,#$20,*
;WAIT FOR IBB FLAG TO CLEAR
;SET TRANSMIT AND MASTER MODE
;i.e. GENERATE START CONDITION
;TRANSMIT THE CALLING
;ADDRESS, D0=R/W
;WAIT FOR IBB FLAG TO SET
15.7.3 Post-Transfer Software Response
Transmission or reception of a byte will set the data transferring bit (TCF)
to 1, which indicates one byte communication is finished. The IIC Bus
interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt
function is enabled during initialization by setting the IBIE bit. Software
must clear the IBIF bit in the interrupt routine first. The TCF bit will be
cleared by reading from the IIC Bus Data I/O Register (IBDR) in receive
mode or writing to IBDR in transmit mode.
Software may service the IIC I/O in the main program by monitoring the
IBIF bit if the interrupt function is disabled. Note that polling should
monitor the IBIF bit rather than the TCF bit since their operation is
different when arbitration is lost.
Note that when an interrupt occurs at the end of the address cycle the
master will always be in transmit mode, i.e. the address is transmitted. If
master receive mode is required, indicated by R/W bit in IBDR, then the
Tx/Rx bit should be toggled at this stage.
During slave mode address cycles (IAAS=1) the SRW bit in the status
register is read to determine the direction of the subsequent transfer and
the Tx/Rx bit is programmed accordingly. For slave mode data cycles
(IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register
should be read to determine the direction of the current transfer.
MC68HC912DG128 — Rev 3.0
MOTOROLA
Inter-IC Bus
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Technical Data
291