MC68HC912DG128 Datasheet, PDF (256/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Multiple Serial Interface
PT — Parity Type
If parity is enabled, this bit determines even or odd parity for both the
receiver and the transmitter.
0 = Even parity is selected. An even number of ones in the data
character causes the parity bit to be zero and an odd number
of ones causes the parity bit to be one.
1 = Odd parity is selected. An odd number of ones in the data
character causes the parity bit to be zero and an even number
of ones causes the parity bit to be one.
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RESET:
0
0
0
0
0
0
0
0
SC0CR2/SC1CR2 — SCI Control Register 2
$00C3/$00CB
Read or write anytime.
TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt will be requested whenever the TDRE status flag
is set.
TCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt will be requested whenever the TC status flag is
set.
RIE — Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled, RAF interrupt in WAIT mode
disabled
1 = SCI interrupt will be requested whenever the RDRF or OR
status flag is set, or when RAF is set while in WAIT mode with
VDDPLL high.
ILIE — Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt will be requested whenever the IDLE status flag
is set.
Technical Data
256
MC68HC912DG128 — Rev 3.0
Multiple Serial Interface
For More Information On This Product,
Go to: www.freescale.com
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