MC68HC912DG128 Datasheet, PDF (414/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Appendix: CGM Practical Aspects
Table 20-2. Suggested 8MHz Synthesis PLL Filter Elements (Acquisition Mode)
Reference
[MHz]
0.614
0.614
0.614
0.614
0.8
0.8
0.8
0.8
1
1
1
1
1.6
1.6
1.6
1.6
2
2
2
2
2.66
2.66
2.66
2.66
4
4
4
4
SYNR
$0C
$0C
$0C
$0C
$09
$09
$09
$09
$07
$07
$07
$07
$05
$05
$05
$05
$03
$03
$03
$03
$02
$02
$02
$02
$01
$01
$01
$01
Fbus
[MHz]
7.98
7.98
7.98
7.98
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
C₀ [nF] R₀ [kΩ] C_p [nF]
1000
0.43
100
47
2
4.7
10
4.3
1.0
3.3
7.5
0.33
2200
0.27
220
100
1.2
10
22
2.4
2.2
4.7
5.6
0.47
2200
0.22
220
100
1.0
10
2.
2.2
2.2
4.7
4.7
0.47
3300
0.15
330
100
0.82
10
33
1.5
3.3
10
2.7
1.0
4700
0.1
470
220
0.51
22
47
1.0
4.7
10
2.4
1.0
2200
0.12
220
220
0.43
22
47
1.0
4.7
10
2
1.0
2200
0.1
220
330
0.27
33
100
0.51
10
22
1.0
2.2
Loop
Bandwidth
[kHz]
1.2
5.5
12
21
0.9
4.4
9.3
20.1
1
4.8
10.4
22.5
1.1
6.2
10.7
19.5
1
4.6
10
21.8
1.7
5.3
11.6
25.1
2.1
5.4
9.7
20.8
Bandwidth
Limit [kHz]
157
157
157
157
201
201
201
201
251
251
251
251
402
402
402
402
502
502
502
502
668
668
668
668
1005
1005
1005
1005
Technical Data
414
MC68HC912DG128 — Rev 3.0
Appendix: CGM Practical Aspects
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