MC68HC912DG128 Datasheet, PDF (271/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Multiple Serial Interface
Port S
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
SP0DR — SPI Data Register
$00D5
Read anytime (normally only after SPIF flag set). Write anytime (see
WCOL write collision flag).
Reset does not affect this address.
This 8-bit register is both the input and output register for SPI data.
Reads of this register are double buffered but writes cause data to be
written directly into the serial shifter. In the SPI system the 8-bit data
register in the master and the 8-bit data register in the slave are linked
by the MOSI and MISO wires to form a distributed 16-bit register. When
a data transfer operation is performed, this 16-bit register is serially
shifted eight bit positions by the SCK clock from the master so the data
is effectively exchanged between the master and the slave. Note that
some slave devices are very simple and either accept data from the
master without returning data to the master or pass data to the master
without requiring data from the master.
14.6 Port S
In all modes, port S bits PS[7:0] can be used for either general-purpose
I/O, or with the SCI and SPI subsystems. During reset, port S pins are
configured as high-impedance inputs (DDRS is cleared).
PORTS — Port S Data Register
Pin
Function
Bit 7
PS7
SS
CS
6
PS6
SCK
5
PS5
MOSI
MOMI
4
PS4
MISO
SISO
3
PS3
TXD1
2
PS2
RXD1
1
PS1
TXD0
Bit 0
PS0
RXD0
$00D6
Read anytime (inputs return pin level; outputs return pin driver input
level). Write data stored in internal latch (drives pins only if configured for
output). Writes do not change pin state when pin configured for SPI or
SCI output.
MC68HC912DG128 — Rev 3.0
MOTOROLA
Multiple Serial Interface
For More Information On This Product,
Go to: www.freescale.com
Technical Data
271