MC68HC912DG128 Datasheet, PDF (430/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Appendix: MC68HC912DG128A EEPROM
22.4 EEPROM Control Registers
EEDIVH — EEPROM Modulus Divider
$00EE
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
EEDIV9 EEDIV8
RESET:
0
0
0
0
0
0
—⁽¹⁾
—⁽¹⁾
1. Loaded from SHADOW word.
EEDIVL — EEPROM Modulus Divider
RESET:
Bit 7
EEDIV7
—⁽¹⁾
6
EEDIV6
—⁽¹⁾
5
EEDIV5
—⁽¹⁾
1. Loaded from SHADOW word.
4
EEDIV4
—⁽¹⁾
3
EEDIV3
—⁽¹⁾
2
EEDIV2
—⁽¹⁾
1
EEDIV1
—⁽¹⁾
Bit 0
EEDIV0
—⁽¹⁾
$00EF
EEDIV[9:0] — Prescaler divider
Loaded from SHADOW word at reset.
Read anytime. Write once in normal modes (SMODN =1) if EELAT =
0 and anytime in special modes (SMODN =0) if EELAT = 0.
The prescaler divider is required to produce a self-time clock with a
fixed frequency around 28.6 Khz for the range of oscillator
frequencies. The divider is set so that the oscillator frequency can be
divided by a divide factor that can produce a 35 µs +/- 2µs pulse.
CAUTION:
An incorrect or uninitialized value on EEDIV can result in overstress of
EEPROM array during program/erase operation. It is also strongly
recommend not to program EEPROM with oscillator frequencies less
than 250 Khz.
The EEDIV value is determined by the following formula:
EEDIV = INT[EXTALi (hz) x 35×10–6 + 0.5]
NOTE: INT[A] denotes the round down integer value of A. Program/erase cycles
will not be activated when EEDIV = 0.
Technical Data
430
MC68HC912DG128 — Rev 3.0
Appendix: MC68HC912DG128A EEPROM
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