MC68HC912DG128 Datasheet, PDF (112/452 Pages) Motorola, Inc – Microcontrollers

Flash Memory
Freescale Semiconductor, Inc.
VTCK — V_T Check Test Enable
When VTCK is set, the Flash EEPROM module uses the V_FP pin to
control the control gate voltage; the sense amp time-out path is
disabled. This allows for indirect measurements of the bit cells
program and erase threshold. If V_FP < V_ZBRK (breakdown voltage) the
control gate will equal the V_FP voltage.
If V_FP > V_ZBRK the control gate will be regulated by the following
equation:
Vcontrol gate = V_ZBRK + 0.44 × (V_FP − V_ZBRK)
0 = V_T test disable
1 = V_T test enable
STRE — Spare Test Row Enable
The spare test row consists of one Flash EEPROM array row. The
reserved word at location 31 contains production test information
which must be maintained through several erase cycles. When STRE
is set, the decoding for the spare test row overrides the address lines
which normally select the other rows in the array.
0 = LIB accesses are to the Flash EEPROM array
1 = Spare test row in array enabled if SMOD is active
MWPR — Multiple Word Programming
Used primarily for testing, if MWPR = 1, the two least-significant
address lines ADDR[1:0] will be ignored when programming a Flash
EEPROM location. The word location addressed if ADDR[1:0] = 00,
along with the word location addressed if ADDR[1:0] = 10, will both be
programmed with the same word data from the programming latches.
This bit should not be changed during programming.
0 = Multiple word programming disabled
1 = Program 32 bits of data
Technical Data
112
MC68HC912DG128 — Rev 3.0
Flash Memory
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