MC68HC912DG128 Datasheet, PDF (209/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Capture Timer
Introduction
M clock
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
÷ 1, 2, ..., 128
Prescaler
16-bit Free-running
16 BIT MAmINaiTnIMtimEeRr
M clock
÷ 1, 4, 8, 16
Prescaler
Pin logic
Pin logic
Pin logic
Pin logic
Delay counter _EDG0
Delay counter _EDG1
Delay counter _EDG2
Delay counter _EDG3
Comparator
TC0 capture/compare register
TC0H hold register
Comparator
TC1 capture/compare register
TC1H hold register
Comparator
TC2 capture/compare register
TC2H hold register
Comparator
TC3 capture/compare register
TC3H hold register
16-bit load register
16-bit modulus
down counter
0 ^RESET
PAC0
PA0H hold register
0 ^RESET
PAC1
PA1H hold register
0 ^RESET
PAC2
PA2H hold register
0 ^RESET
PAC3
PA3H hold register
Pin logic
EDG4
MUX
EDG0
Comparator
TC4 capture/compare register
ICLAT, LATQ, BUFEN
(force latch)
Pin logic
EDG5
MUX
EDG1
Comparator
TC5 capture/compare register
Write $0000
to modulus counter
Pin logic
EDG6
MUX
EDG2
Comparator
TC6 capture/compare register
LATQ
(MDC latch enable)
Pin logic
EDG7
MUX
EDG3
Comparator
TC7 capture/compare register
Figure 13-1. Timer Block Diagram in Latch Mode
MC68HC912DG128 — Rev 3.0
MOTOROLA
Enhanced Capture Timer
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Technical Data
209