MC68HC912DG128 Datasheet, PDF (227/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR
register is set.
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC0 — Timer Input Capture/Output Compare Register 0
1
Bit 0
9
Bit 8
1
Bit 0
$0090–$0091
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC1 — Timer Input Capture/Output Compare Register 1
1
Bit 0
9
Bit 8
1
Bit 0
$0092–$0093
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC2 — Timer Input Capture/Output Compare Register 2
1
Bit 0
9
Bit 8
1
Bit 0
$0094–$0095
Bit 7
6
5
4
3
2
1
Bit 15
14
13
12
11
10
9
Bit 7
6
5
4
3
2
1
TC3 — Timer Input Capture/Output Compare Register 3
MC68HC912DG128 — Rev 3.0
MOTOROLA
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
Bit 0
Bit 8
Bit 0
$0096–$0097
Technical Data
227