MC68HC912DG128 Datasheet, PDF (175/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Functions
Limp-Home and Fast STOP Recovery modes
LOCK — Locked Phase Lock Loop Circuit
Regardless of the bandwidth control mode (automatic or manual):
0 = PLL VCO is not within the desired tolerance of the target
frequency.
1 = After the phase lock loop circuit is turned on, indicates the PLL
VCO is within the desired tolerance of the target frequency.
Write has no effect on LOCK bit. This bit is cleared in limp-home mode as
the lock detector cannot operate without the reference frequency.
LHIF — Limp-Home Interrupt Flag
0 = No change in LHOME bit.
1 = LHOME condition has changed, either entered or exited limp-
home mode.
To clear the flag, write one to this bit in PLLFLG.
LHOME — Limp-Home Mode Status
0 = MCU is operating normally, with EXTALi clock available for
generating clocks or as PLL reference.
1 = Loss of reference clock. CGM delivers PLL VCO limp-home
frequency to the MCU.
For Limp-Home mode, see Limp-Home and Fast STOP Recovery modes.
Bit 7
6
5
4
3
2
LOCKIE PLLON
AUTO
ACQ
0
PSTP
RESET:
0
—⁽¹⁾
1
0
0
0
PLLCR — PLL Control Register
1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low.
2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low.
1
LHIE
0
Bit 0
NOLHM
—⁽²⁾
$003C
Read and write anytime. Exceptions are listed below for each bit.
LOCKIE — PLL LOCK Interrupt Enable
0 = PLL LOCK interrupt is disabled
1 = PLL LOCK interrupt is enabled
Forced to 0 when VDDPLL=0.
MC68HC912DG128 — Rev 3.0
MOTOROLA
Clock Functions
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Technical Data
175