MC68HC912DG128 Datasheet, PDF (173/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Functions
Limp-Home and Fast STOP Recovery modes
Table 11-2. Summary of Pseudo STOP Mode Exit Conditions
Mode
Pseudo-STOP exit in Limp Home
mode with Delay
Pseudo-STOP exit
in Limp Home mode without
Delay (Fast Stop Recovery)
Pseudo-STOP exit without Limp
Home mode, clock monitor
enabled
Pseudo-STOP exit without Limp
Home mode, clock monitor
disabled, with Delay
Pseudo-STOP exit without Limp
Home mode, clock monitor
disabled, without Delay
Conditions
NOLHM=0
CME=X
DLY=1
NOLHM=0
CME=X
DLY=0
NOLHM=1
CME=1
DLY=X
NOLHM=1
CME=0
DLY=1
NOLHM=1
CME=0
DLY=0
Summary
CPU exits stop in limp home mode and oscillator running. If
the oscillator fails during pseudo-STOP and then recovers
there is a possibility of code runaway as the clock monitor
circuit can be misled by EXTALi clock into reporting a
good signal before it has fully stabilised
This mode is not recommended as it is possible that the
initial VCO clock frequency may be high enough to cause
code runaway.
When a STOP instruction is executed the MCU resets via
the clock monitor reset vector.
Oscillator starts operation following 4096 XCLK cycles
(actual controlled by SLOW mode divider).
This mode is only recommended for use with an external
clock source.
11.6.14 PLL Register Descriptions
Bit 7
6
0
0
RESET:
0
0
SYNR — Synthesizer Register
5
SYN5
0
4
SYN4
0
3
SYN3
0
2
SYN2
0
1
SYN1
0
Bit 0
SYN0
0
$0038
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
MC68HC912DG128 — Rev 3.0
MOTOROLA
Clock Functions
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Technical Data
173