MC68HC912DG128 Datasheet, PDF (228/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Capture Timer
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC4 — Timer Input Capture/Output Compare Register 4
1
Bit 0
9
Bit 8
1
Bit 0
$0098–$0099
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC5 — Timer Input Capture/Output Compare Register 5
1
Bit 0
9
Bit 8
1
Bit 0
$009A–$009B
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC6 — Timer Input Capture/Output Compare Register 6
1
Bit 0
9
Bit 8
1
Bit 0
$009C–$009D
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC7 — Timer Input Capture/Output Compare Register 7
1
Bit 0
9
Bit 8
1
Bit 0
$009E–$009F
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when
a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Technical Data
228
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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