MC68HC912DG128 Datasheet, PDF (260/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Multiple Serial Interface
Bit 7
6
5
4
3
2
1
Bit 0
0I
0
0
0
0
0
0
RAF
RESET:
0
0
0
0
0
0
0
0
SC0SR2/SC1SR2 — SCI Status Register 2
$00C5/$00CD
Read anytime. Write has no meaning or effect.
RAF — Receiver Active Flag
This bit is controlled by the receiver front end. It is set during the RT1
time period of the start bit search. It is cleared when an idle state is
detected or when the receiver circuitry detects a false start bit
(generally due to noise or baud rate mismatch).
0 = A character is not being received
1 = A character is being received
If enabled with RIE = 1, RAF set generates an interrupt when
VDDPLL is high while in WAIT mode.
Bit 7
6
5
4
3
2
1
Bit 0
R8
T8
0
0
0
0
0
0
RESET:
—
—
—
—
—
—
—
—
SC0DRH/SC1DRH — SCI Data Register High
$00C6/$00CE
Bit 7
6
5
R7/T7
R6/T6
R5/T5
RESET:
—
—
—
SC0DRL/SC1DRL — SCI Data Register Low
4
R4/T4
—
3
R3/T3
—
2
R2/T2
—
1
R1/T1
—
Bit 0
R0/T0
—
$00C7/$00CF
Bit 7
6
5
4
3
2
1
Bit 0
R8
T8
0
0
0
0
0
0
RESET:
—
—
—
—
—
—
—
—
SC0DRH/SC1DRH — SCI Data Register High
$00C6/$00CE
Technical Data
260
MC68HC912DG128 — Rev 3.0
Multiple Serial Interface
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