MC68HC912DG128 Datasheet, PDF (216/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Capture Timer
If the corresponding NOVWx bit of the ICOVW register is cleared, with a
new occurrence of a capture, the value of the IC register will be transferred
to its holding register and the IC register memorizes the new timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register or its holding register cannot be written by an event unless they
are empty (see IC Channels).
In queue mode, reads of holding register will latch the corresponding
pulse accumulator value to its holding register.
13.3.2 Pulse Accumulators
There are four 8-bit pulse accumulators with four 8-bit holding registers
associated with the four IC buffered channels. A pulse accumulator
counts the number of active edges at the input of its channel.
The user can prevent 8-bit pulse accumulators counting further than $FF
by PACMX control bit in ICSYS ($AB). In this case a value of $FF means
that 255 counts or more have occurred.
Each pair of pulse accumulators can be used as a 16-bit pulse accumulator.
There are two modes of operation for the pulse accumulators.
13.3.2.1 Pulse Accumulator latch mode
The value of the pulse accumulator is transferred to its holding register
when the modulus down-counter reaches zero, a write $0000 to the
modulus counter or when the force latch control bit ICLAT is written.
At the same time the pulse accumulator is cleared.
13.3.2.2 Pulse Accumulator queue mode
When queue mode is enabled, reads of an input capture holding register
will transfer the contents of the associated pulse accumulator to its
holding register.
At the same time the pulse accumulator is cleared.
Technical Data
216
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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