MC68HC912DG128 Datasheet, PDF (130/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
EEPROM Memory
EETST — EEPROM Test
Bit 7
6
5
4
3
2
EEODD EEVEN MARG EECPD EECPRD
0
RESET:
0
0
0
0
0
0
1
EECPM
0
Bit 0
0
0
$00F2
Read anytime. Write in special modes only (SMODN = 0). These bits are
used for test purposes only. In normal modes the bits are forced to zero.
EEODD — Odd Row Programming
0 = Odd row bulk programming/erasing is disabled.
1 = Bulk program/erase all odd rows.
EEVEN — Even Row Programming
0 = Even row bulk programming/erasing is disabled.
1 = Bulk program/erase all even rows.
MARG — Program and Erase Voltage Margin Test Enable
0 = Normal operation.
1 = Program and Erase Margin test.
This bit is used to evaluate the program/erase voltage margin.
EECPD — Charge Pump Disable
0 = Charge pump is turned on during program/erase.
1 = Disable charge pump.
EECPRD — Charge Pump Ramp Disable
Known to enhance write/erase endurance of EEPROM cells.
0 = Charge pump is turned on progressively during program/erase.
1 = Disable charge pump controlled ramp up.
EECPM — Charge Pump Monitor Enable
0 = Normal operation.
1 = Output the charge pump voltage on the IRQ/V_PP pin.
Technical Data
130
MC68HC912DG128 — Rev 3.0
EEPROM Memory
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Go to: www.freescale.com
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